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| CXD2073Q Digital Comb Filter (NTSC) Description The CXD2073Q is an adaptive comb filter compatible with NTSC system, and provide high-precision Y/C separation with a single chip. Features * Y/C separation by adaptive processing * Horizontal aperture compensation circuit * 8-bit A/D converter (1 channel) * 8-bit D/A converter (2 channels) * One 1H delay line * 4 PLL * Clamp circuit Absolute Maximum Ratings (Ta = 25C, VSS = 0V) * Supply voltage DVDD VSS - 0.5 to +7.0 V DAVD VSS - 0.5 to +7.0 V ADVD VSS - 0.5 to +7.0 V PLVD VSS - 0.5 to +7.0 V * Input voltage VI VSS - 0.5 to VDD +0.5 V * Output voltage VO VSS - 0.5 to VDD +0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage DVDD 5.0 0.25 DAVD 5.0 0.25 ADVD 5.0 0.25 PLVD 5.0 0.25 * Operating temperature Topr -20 to +75 32 pin QFP (Plastic) Structure Silicon gate CMOS IC Applications Y/C separation for color TVs and VCRs V V V V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97411-PS CXD2073Q Pin Configuration (Top View) TST1 TST2 DVDD 24 FIN 25 CKSL 26 CPO 27 VCV 28 PLVD 29 PLVS 30 CLPEN 31 CLPO 32 1 23 22 21 20 19 18 DVDD 17 16 APCN 15 MOD1 14 MOD2 13 INIT 12 IRF 11 VB 10 9 VG VRF 2 3 4 5 6 7 ADVD ADIN AYO NC Block Diagram DAVD ADVS DAVS ACO TST3 8 DVSS NC DVSS DL D/A 7 AYO ADIN 1 A/D 1H Chroma Output Block D/A 4 ACO CLPO 32 Clamp Logic Operation Block 1/4 FIN 25 VCO SEL Internal clock 27 28 26 VCV -2- CKSL CPO CXD2073Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Symbol ADIN ADVS ADVD ACO NC DAVD AYO DAVS VRF VG VB IRF INIT MOD2 MOD1 I/O I -- -- O -- -- O -- I O O O I I I Description Comb filter analog input (A/D converter input) Analog ground for A/D converter Analog power supply for A/D converter (+5V) Analog chroma signal output Leave this pin open. Analog power supply for D/A converter (+5V) Analog luminance signal output Analog ground for D/A converter D/A converter VRF (reference voltage). Sets the full-scale value for D/A converter. Connect to DAVD via a capacitor of approximately 0.1F. Connect to DAVS via a capacitor of approximately 0.1F. Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin. Test. Normally, fix to Low. Y/C separation status setting pins MOD2 MOD1 L L Adaptive processing mode L H BPF separation fixed mode H L Y through mode H H Simple comb mode Aperture compensation switching L: Aperture compensation OFF H: Aperture compensation ON Test. Normally, leave this pin open. Digital ground Digital power supply (+5V) Leave this pin open. Digital power supply (+5V) Digital ground Test. Normally, leave this pin open. Test. Normally, fix to Low. FSC clock input. Input burst-locked fsc when PLL is used. Input burst-locked 4fsc when PLL is not used. PLL control. L: Clock, which is input to FIN, is supplied internally when PLL is not used. H: 4fsc of VCO oscillation output is supplied to internal clock when PLL is used. Phase comparison output for built-in PLL. Leave this pin open when PLL is not used. Built-in VCO oscillation control voltage input. Connect to PLVS when PLL is not used. PLL power supply (+5 V) PLL ground Clamp enable L: Clamp function is enabled. H: Clamp function is disenabled. Connect to ADIN when clamp circuit is used. Leave this pin open when clamp circuit is not used. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 APCN TST3 DVSS DVDD NC DVDD DVSS TST2 TST1 FIN CKSL CPO VCV PLVD PLVS CLPEN CLPO I O -- -- -- -- -- O I I I O I -- -- I O -3- CXD2073Q Electrical Characteristics Item Symbol DVDD Supply voltage ADVD DAVD PLVD Operating temperature Supply current High level input voltage Low level input voltage High level output voltage Low level output voltage Logical Vth Input voltage Feedback resistor Topr IDD VIH VIL VOH VOL LVth VIN RFB FIN (Pin 25) -- -- (VDD = 5 0.25V, VSS = 0V, Ta = -20 to +75C) Conditions Min. Typ. Max. Unit 4.75 5.0 5.25 V -20 -- VDD x 0.7 VSS VDD - 0.8 VSS -- 0.5 250k -- -- -- -- -- -- VDD/2 -- 1M +75 60 VDD VDD x 0.3 VDD 0.4 -- VDD 2.5M C mA V V V V V Vp-p Clock 14MHz CMOS level CMOS level IOH = -2mA IOL = 4mA A/D Converter Characteristics Item Resolution Max. conversion speed Analog input band width Input bias Output data delay Differential linearity error Integral linearity error n fmax BW BOTTOM TOP - BOTTOM tpd ED EL -3dB Symbol Conditions Min. -- 14.3 -- 0.48 1.96 -- -1.0 -3.0 (VDD = 5V, Ta = 25C, f = 10MHz) Typ. 8 -- 18 0.52 2.08 -- -- -- Max. -- -- -- 0.56 2.22 45 +1.0 +3.0 Unit bit MSPS MHz V V ns LSB LSB D/A Converter Characteristics Item Resolution Max. conversion speed Differential linearity error Integral linearity error Output full-scale voltage Output full-scale current Output offset voltage Precision guaranteed output voltage range n fmax ED EL VFS IFS VOS VOC Symbol (VDD = 5V, VRF = 2V, IRF = 3.3k, R = 200, Ta = 25C, f = 10MHz) Conditions Min. -- -- -- -- -- -- -- -- -4- 14.3 -0.8 -2.0 1.805 -- -- 1.8 Typ. 8 -- -- -- 1.90 9.5 -- -- Max. -- -- +0.8 +2.0 1.995 15 1.0 2.1 Unit bit MSPS LSB LSB V mA mV V CXD2073Q Clamp Item Clamp level1 1 Sync tip clamp CLV Symbol Conditions Min. -- (VDD = 5V, Ta = 25C, f = 10MHz) Typ. 0.67 Max. -- Unit V Description of Functions * Horizontal aperture compensation Compensates aperture degradation accompanied by D/A conversion. This compensation is effective for the following modes; adaptive processing, Y through, and simple comb modes. * Adaptive processing mode This mode detects interline correlation, switches between comb filter processing and BPF processing, and operates Y/C separation. * Y through mode The composite video signal input from ADIN (Pin 1) is A/D converted. It is also D/A converted, and then output from AYO (Pin 7). At this time, the output of ACO (Pin 4) is the same output as that of adaptive processing mode. * BPF mode C signal is generated by passing composite video signal through BPF. Y output is a signal in which the C signal generated is subtracted from input composite video signal. * Simple comb mode Y/C separation is operated by the comb filter processing forcibly. Modes Adaptive processing mode Y through mode BPF mode Simple comb mode MOD1 (Pin 15) L L H H MOD2 (Pin 14) L H L H -5- CXD2073Q Application Circuit for D/A Converter 6 10 0.1 8 DAVD AYO 7 200 (R) 3k Y OUT DAVS VRF 9 2k 3.3k 0.1 IRF 12 (R') ACO 4 200 (R) 0.1 C OUT VG 10 0.1 VB 11 : analog power supply 5V : analog ground * Method of selecting output resistance The CXD2073Q has a built-in current output-type D/A converter. To obtain the output voltages, connect resistors to AYO and ACO pins. VFS = IFS x R Here, VFS is output full-scale voltage, IFS is output full-scale current, and R is the output resistance connected to each IO. In addition, connect a resistance of 16 times the output resistor to the reference current pin IRF. In the case where the value comes to be impractical, use a value of resistance as close to the value calculated as possible. At that time, VFS = VRF x 16 x R/R'. R is the output resistance connected to each IO, R' is the resistance connected to IRF, and VRF is the VRF pin voltage. Power consumption can be reduced by using higher resistance values, but then glitch energy and data settling time increase contrastingly. Select optimum resistance values according to the system applications. In case of the circuit above, VFS = 2 [V] x 16 x 0.2k/3.3k 1.93 [V], IFS = 1.93/0.2k 9.65 [mA]. Notes on Operation * Power supply, ground Separate the analog and digital systems around the device to reduce noise effect. Both analog and digital VDD are respectively bypassed to VSS as close to these VDD and VSS pins as possible through ceramic capacitors of approximately 0.1F. Also, layout the power supply and ground pattern of the board substrate as wide as possible to lower impedance. * Clock Use the burst-locked clock. Separate the clock line on the board substrate as far as possible from analogrelated pins, analog power supply, and analog ground. -6- CXD2073Q External Connection D5V 0.1 0.1 24 23 22 21 20 19 18 17 TST2 DVDD DVDD TST1 Clock H 560 L 0.001 25 FIN 56k DVSS TST3 DVSS NC 26 CKSL 27 CPO 16 APCN MOD1 15 MOD2 14 INIT 13 3.3k IRF 12 0.1 VB 11 0.1 VG 10 0.022 A5V 0.1 30 PLVS H L 31 CLPEN 28 VCV 29 PLVD H L H L H L A5V 10k 10 ADVD DAVD ADIN ADVS ACO NC 1 2 3 4 5 6 AYO 7 10 0.1 200 A5V COUT 0.1 200 A5V YOUT analog power supply analog ground digital power supply digital ground Composite Video In Selected Pins Pin No. 14 15 16 26 31 Symbol MOD2 MOD1 APCN CKSL CLPEN H L Combination of MOD1 and MOD2 (MOD1, MOD2) = (L, L) Normal mode (L, H) Y through mode (H, L) BPF mode (L, H) Simple comb mode Horizontal aperture compensation ON Internal quadruple PLL is used Internal clamp is not used Horizontal aperture compensation OFF Internal quadruple PLL is not used Internal clamp is used -7- DAVS 8 32 CLPO VRF 9 CXD2073Q Application Circuit (1) In case that fsc is used as clock D5V X'tal 3.58MHz 24 23 0.1 0.1 22 21 20 19 18 17 TST2 DVDD DVDD TST1 Clock Generator 0.001 25 FIN DVSS TST3 DVSS Burst-locked Clock H 560 L NC 26 CKSL 56k 27 CPO 16 APCN MOD1 15 MOD2 14 INIT 13 3.3k IRF 12 0.1 VB 11 0.1 VG 10 0.022 28 VCV A5V 29 PLVD 0.1 30 PLVS H L 31 CLPEN H L H L H L A5V 5k 10 ADVD DAVD ADVS ADIN ACO NC 1 2 3 4 5 6 AYO 7 0.1 10 200 A5V COUT LPF 0.1 200 A5V YOUT analog power supply analog ground digital power supply digital ground H: CMOS High level Composite Video In DAVS 8 32 CLPO VRF 9 L: CMOS Low level Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -8- CXD2073Q (2) In case that 4fsc is used as clock D5V X'tal 14.3MHz 24 23 0.1 0.1 22 21 20 19 18 17 TST2 DVDD DVDD TST1 Clock Generator 0.001 25 FIN DVSS TST3 DVSS Burst-locked Clock H L NC 26 CKSL 27 CPO 28 VCV 16 APCN MOD1 15 MOD2 14 INIT 13 3.3k IRF 12 0.1 VB 11 0.1 VG 10 H L H L H L A5V 0.1 29 PLVD 30 PLVS H L 31 CLPEN A5V 5k 10 ADVD ADVS DAVD ADIN ACO NC 1 2 3 4 5 6 AYO 7 0.1 10 200 A5V COUT LPF 0.1 200 A5V YOUT analog power supply analog ground digital power supply digital ground H: CMOS High level Composite Video In DAVS 8 32 CLPO VRF 9 L: CMOS Low level Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -9- CXD2073Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15 0.1 25 16 32 9 + 0.2 0.1 - 0.1 1 0.8 + 0.15 0.3 - 0.1 8 + 0.1 0.127 - 0.05 0 to 10 0.12 M PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g - 10 - 0.50 (8.0) |
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